1. Field of the Invention
Generally, the present invention relates to the field of fabricating microstructures, such as integrated circuits, micromechanical structures and the like, and, more particularly, to the formation of an ultra-thin dielectric layer having increased resistance against migration of charge carriers through the dielectric layer.
2. Description of the Related Art
Presently, microstructures are integrated into a wide variety of products. One example in this respect is the employment of integrated circuits that, due to their relatively low cost and high performance, are increasingly used in many types of devices, thereby allowing superior control and operation of those devices. Due to economic reasons, manufacturers of microstructures, such as integrated circuits, are confronted with the task of steadily improving performance of these microstructures with every new generation appearing on the market. However, these economic constraints not only require improving the device performance but also demand a reduction in size so as to provide more functionality of the integrated circuit per unit chip area. Thus, in the semiconductor industry, ongoing efforts are being made to reduce the feature sizes of feature elements. In present day technologies, the critical dimensions of these elements approach 0.1 xcexcm and less. In producing circuit elements of this order of magnitude, process engineers are, along with many other issues especially arising from the reduction of feature sizes, faced with the task of providing extremely thin dielectric layers on an underlying material layer, wherein certain characteristics of the dielectric layer, such as permittivity and/or resistance against charge carrier tunneling and the like, have to be improved without sacrificing the physical properties of the underlying material layer.
One important example in this respect is the formation of ultra-thin gate insulation layers of field effect transistors, such as MOS transistors. The gate dielectric of a transistor has an impact on the performance of the transistor. As is commonly known, reducing the size of a field effect transistor, that is reducing the length of a conductive channel that forms in a portion of a semiconductor region by applying a control voltage to a gate electrode formed on the gate insulation layer, also requires the reduction of the thickness of the gate insulation layer to maintain the required capacitive coupling from the gate electrode to the channel region. Currently, most of the highly sophisticated integrated circuits, such as CPUs, memory chips and the like, are based on silicon and, therefore, silicon dioxide has preferably been used as the material for the gate insulation layer due to the well-known and superior characteristics of the silicon dioxide/silicon interface. For a channel length on the order of 100 nm and less, however, the thickness of the gate insulation layer has to be reduced to about 2 nm in order to maintain the required controllability of the transistor operation. Steadily decreasing the thickness of the silicon dioxide gate insulation layer, however, leads to an increased leakage current therethrough, thereby resulting in an unacceptable increase of static power consumption as the leakage current exponentially increases for a linear reduction of the layer thickness.
Therefore, great efforts are presently being made to replace silicon dioxide by a dielectric exhibiting a significantly higher permittivity so that a thickness thereof may be remarkably higher than the thickness of a corresponding silicon dioxide layer providing the same capacitive coupling. A thickness for obtaining a specified capacitive coupling will also be referred to as capacitive equivalent thickness and determines the thickness that would be required for a silicon dioxide layer. It turns out, however, that it is difficult to incorporate high-k materials into the conventional integration process and, more importantly, the provision of a high-k material as a gate insulation layer seems to have a significant influence on the carrier mobility in the underlying channel region, thereby remarkably reducing the carrier mobility and thus the drive current capability. Hence, although an improvement of the static transistor characteristics may be obtained by providing a thick high-k material, at the same time an unacceptable degradation of the dynamic behavior presently makes this approach less than desirable.
A different approach that is currently favored is the employment of an integrated silicon oxide/nitride layer stack that may reduce the gate leakage current by 0.5-2.0 orders of magnitude while maintaining compatibility with standard CMOS process techniques. It has been found that the reduction of the gate leakage current mainly depends upon the nitrogen concentration incorporated into the silicon dioxide layer by means of plasma nitridation. Although this approach seems to relax the issue of gate dielectric leakage for the present circuit generation, this approach does not seem to allow further aggressive dielectric thickness scaling required for future device generations. In addition, this solution may be difficult to be designed so as to be compatible with sophisticated CMOS processes. To more clearly demonstrate the problems involved in the conventional process technique, a typical process flow for forming a gate insulation layer, including a silicon dioxide/nitride layer, will now be described with reference to FIGS. 1a-1e. 
In FIG. 1a, a semiconductor device 100 comprises a silicon substrate 101, in which an active region 103 is defined by shallow trench isolations 102. A thin dielectric base layer 110, for example formed of a grown oxide layer, covers the active region 103. Moreover, the semiconductor device 100 is exposed to a nitrogen-containing plasma indicated by reference sign 104.
Typically, the semiconductor device 100 may be formed according to the following process sequence. After formation of the shallow trench isolations 102 and various implantation steps to generate a required well dopant profile (not shown) in the active region 103, the dielectric base layer 110 is formed by a conventional oxidation process or by a rapid thermal oxidation process. Subsequently, the semiconductor device 100 is exposed to the nitrogen-containing plasma 104 to introduce nitrogen ions into the silicon dioxide layer 110 to improve, as explained above, the resistance of the dielectric base layer 110 against charge carrier migration. An energy of the ions in the nitrogen-containing plasma 104 is substantially determined by the difference between the plasma potential and the floating potential of the semiconductor device 100, wherein this voltage is difficult to adjust or may not be adjustable at all.
As is well known, nitrogen atoms, introduced into the active region 103 and, thus, into the channel region of the transistor device to be formed, significantly affect the electrical characteristics of the transistor device in that both the crystallinity of the active region 103 is deteriorated and the charge carrier mobility is degraded. Consequently, the introduction of nitrogen into the active region 103 has to be suppressed as much as possible in view of a required high transistor performance. On the other hand, a thickness of the dielectric base layer 110 is to be scaled down in conformity with the device dimensions which would, however, at a certain minimum dielectric thickness, lead to an increased penetration of nitrogen ions into the active region 103 during the plasma treating 104. As a consequence, there exists a severe trade-off between the improvement of the transistor device performance by scaling down the dielectric base layer 110 and the device degradation caused by the incorporation of nitrogen into the active region 103. FIGS. 1b-1c will more clearly illustrate this situation.
In FIG. 1b, on the left-hand side, a cut-out of FIG. 1a is schematically illustrated in a magnified view, in which the dielectric base layer 110 includes nitrogen atoms in a concentration profile 112 along a depth direction 111. As is evident from FIG. 1b, a thickness 113 of the dielectric base layer 110 is selected so that a penetration of nitrogen into the underlying active region 103 may be substantially avoided. The right-hand side of FIG. 1b depicts a graph, wherein the concentration profile 112 is plotted versus the depth direction 111. As can be seen from this graph, the nitrogen concentration drops to a very low value, which in the present illustration is idealized as zero, within the thickness 113 of the base layer 110, thereby substantially avoiding any device degradation caused by the reduction of carrier mobility. The situation illustrated in FIG. 1b represents the design thickness 113 in conformity with a desired channel length, which suffices to still allow a substantial blocking of the nitrogen.
FIG. 1c, on the other hand, illustrates the situation when a thickness 113xe2x80x2 of the base layer 110 has to be reduced in conformity with design rules compared to that of FIG. 1b and, therefore, the concentration profile 112 reaches down into the active area 103 as the plasma conditions may be difficult to control to determine or limit the penetration depths of the nitrogen. The right-hand side of FIG. 1c shows a resulting nitrogen concentration 112 with respect to the depth direction 111 and clearly reveals that a significant amount of nitrogen is in the active region 103, to thereby negatively affect the carrier mobility.
FIG. 1d schematically shows the semiconductor device 100 in an advanced manufacturing stage. Drain and source regions 107 are formed within the active region 103 and a gate electrode 106 is formed on the patterned dielectric base layer 110, which is now indicated as 110a, wherein the gate insulation layer 110a has the thickness 113 and a nitrogen concentration profile 112, as shown in FIG. 1b. Moreover, sidewall spacers 105 are formed adjacent to the gate electrode 106.
Typical process steps for forming the semiconductor device 100, as shown in FIG. 1d, include well-known advanced photolithography and etch techniques as well as implantation steps and, thus, a detailed description thereof will be omitted.
FIG. 1e, on the other hand, schematically depicts the semiconductor device 100 having the gate insulation layer 110a with the reduced thickness 113xe2x80x2 as shown in FIG. 1c so that a corresponding residual nitrogen concentration is present within the drain and source regions 107 and the relevant portion of the active region 103.
As a consequence, the prior art processing described above allows a sealing of the thickness 113 of the gate insulation layer 110a to a value that substantially prevents penetration of nitrogen into the active region 103, thereby obtaining improved device performance. However, when design requirements demand a further scaling of the thickness 113 to conform to the corresponding transistor dimensions, i.e., when the design capacitive equivalent thickness requires the thickness 113xe2x80x2, an unacceptable amount of nitrogen is introduced into the surface portion of the active region 103 so that the reduced carrier mobility may result in a device performance degradation.
In view of the above problems, it has been suggested to correspondingly lower the potential of the nitrogen-containing plasma 104 so as to generally reduce the penetration depth of the nitrogen ions. It appears, however, that reducing the potential is limited to a certain minimal value for fundamental considerations. It is, therefore, that the situation described above still maintains even for a minimum plasma potential.
In view of the problems explained above, it is, thus, highly desirable to provide a technique allowing improvement of the resistance of a dielectric layer against migration of charge carriers without unduly negatively affecting the physical characteristics of an underlying material layer, such as the carrier mobility of a silicon layer.
Generally, the present invention is directed to a technique that allows the provision of a dielectric layer having a specified capacitance equivalent thickness, wherein the physical characteristics of an underlying material layer are substantially not affected. A dielectric base layer is formed on the underlying material layer and a required resistance against the passage of charged particles is adjusted by introducing an appropriate concentration of a dielectric dopant, wherein a thickness of the dielectric base layer is selected so as to substantially avoid penetration of the dielectric dopant into the underlying material. By a controlled and slow removal of the doped dielectric base layer, the final thickness thereof is adjusted to the desired capacitance equivalent thickness.
According to one illustrative embodiment of the present invention, a method of forming a dielectric layer on a semiconductor region comprises forming a dielectric base layer having a first predefined thickness and introducing a dielectric dopant into the base layer to increase a resistance against charge carrier migration through the base layer. The first thickness is then reduced to obtain a final thickness that substantially corresponds to a desired design value. In one embodiment, this reduction may be accomplished by an atomic layer etch process.
According to a further illustrative embodiment of the present invention, a method of forming a dielectric layer on a silicon-containing semiconductor region comprises forming a dielectric layer with a first thickness on the silicon-containing semiconductor region and introducing nitrogen into the dielectric layer. Next, a rapid thermal anneal process is carried out in an oxidizing ambient and, subsequently, the first thickness of the dielectric layer is reduced to obtain a final thickness of the dielectric layer corresponding to the predefined capacitance equivalent thickness.
In accordance with still another illustrative embodiment of the present invention, a method of forming a gate insulation layer having a predefined capacitance equivalent thickness comprises providing a substrate including a semiconductor region and a doped dielectric layer formed on the semiconductor region, wherein the dielectric layer has a first thickness. Moreover, the dopants in the dielectric layer are distributed by a rapid thermal anneal process and subsequently material from the doped dielectric layer is removed to obtain a second thickness that substantially corresponds to the predefined capacitance equivalent thickness.